1. Field of the Invention
The invention relates to a method of forming a twin-well for CMOS (Complementary Metal-Oxide-Semiconductor) transistors, and more particularly, to a method of forming a self-aligned planarization twin-well for CMOS transistors by using fewer mask counts than conventional skills.
2. Description of the Prior Art
In the present days, CMOS transistors make more and more devices because the CMOS structures offer a lot of advantages such as low power consumption than NMOS and PMOS transistors. There are many technologies used to fabricate the CMOS transistors, such as p-well, n-well, and twin-well processes. As noted, the twin-well process is the most attractive scheme utilized for fabricating CMOS products because many advantages offered by the twin-well technology. For example, the doping profile of each of the device types can be set independently since the constraint of single-well CMOS does not exist.
All persons skilled in the art know that a planar surface should be prepared before performing sequence processes of forming CMOS transistors. However, it is difficult to obtain a true planarized self-aligned twin-well for CMOS transistors, especially for deep sub-micro ULSI (Ultra-Large-Scale-Integrated) applications that are the main electronic products today (refer to "0.2-.mu.m n-Channel and p-Channel MOSFET's Integrated on Oxidation-Planarized Twin-Tubs" in IEEE Electron Device Lett., vol., EDL-11, p. 500-502, 1996.) A requirement has been arisen to disclose a process for overcoming the aforementioned disadvantages while fabricating CMOS transistors.